Abstract
A programmable logic array (PLA) restructure algorithm which enhances the testability of PLAs is presented. This algorithm transforms the input logic function to a more testable form, and gets a higher testability PLA. The PLA is mapped into a testable structure by adding less extra hardware. In order to get a more testable PLA, the following two strategies are used in the restructure algorithm: (1) Give up the prime cubes. (2) If necessary, partition the more untestable cubes. An efficient program has been implemented in C on a SUN workstation. For 40 benchmark examples, the average overhead reduction is shown to be about 37%. >
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