Restricting writes for energy-efficient hybrid cache in multi-core architectures

Abstract

Emerging non-volatile memory technology Spin Transfer Torque Random Access Memory (STT-RAM) is a good candidate for the Last Level Cache (LLC) on account of high density, good scalability and low power consumption. However, expensive write operation reduces their chances as a replacement of SRAM. To handle these expensive write operations, an STT-RAM/SRAM hybrid cache architecture is proposed that reduces the number of writes and energy consumption of the STT-RAM region in the LLC by considering the existence of private blocks. Our approach allocates dataless entries for such kind of blocks when they are loaded in the LLC on a miss. We make changes in the conventional MESI protocol by adding new states to deal with the dataless entries. Experimental results using full system simulator shows 73% savings in write operations and 20% energy savings compared to an existing policy.