Abstract
Object recognition offers a more general implementation for vision-based applications. This paper reports a resource-efficient recognition coprocessor with embedded cell-based simplified speeded up robust feature descriptor extraction unit and parallel scan-window (SW) recognition engine, applicable for various mobile scenarios and image sensor types. The feature extraction circuitry with pixel-based pipelined architecture describes the target objects among complex backgrounds, only relying on the pixel frequency from the image sensor. A cell-based SW algorithm enables parallelized recognition in multiple SWs and compatibility to different image sizes. The proposed hardware-friendly object-recognition coprocessor was implemented in 65-nm Silicon on thin BOX CMOS technology with 1.26 mm2 core area and can operate down to low supply voltage of 0.5 V. For video graphics array image sizes, the energy efficiency is determined as $910~\mu \text{J}$ per frame at 200 MHz and 1-V supply voltage. The coprocessor’s classification performance is demonstrated for pedestrian and car detection.
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