Abstract

Abstract. Although there is an increase of performance in DSPs, due to its nature of execution a DSP could not perform high-speed data processing on a continuous data stream. In this paper we discuss the hardware implementation of the amplitude and phase detector and the validation block on a FPGA. Contrary to the software implementation which can only process data stream as high as 1.5 MHz, the hardware approach is 225 times faster and introduces much less latency.

Highlights

  • Longitudinal amplitude and phase information of both signals are extracted by the detector and go to the validation block

  • In this paper we focus on the amplitude and phase detector and the validation block which should be able to process two high-speed continuous data streams

  • Our original implementation of the amplitude and phase detector and the validation block which are performed on DSP C6713 is only capable to receive two input data streams as high as 1.5 MHz on each channel Klingbeil (2004)

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Summary

Introduction

Two analog input signals which correspond to the ion states at a specific time are received from the cavity sensors and go to the A/D block (with 14-bit resolution at 28.5 MHz sampling rate). Longitudinal amplitude and phase information of both signals are extracted by the detector and go to the validation block. The validation block outputs the longitudinal amplitude and phase differences of both signals. The corrected signal is used at the end by the controller to control the DDS (Direct Digital Synthesis). In this paper we focus on the amplitude and phase detector and the validation block which should be able to process two high-speed continuous data streams

Longitudinal amplitude and phase
CORDIC
Hardware Realization
Substraction
Validation analysis
Synthesis
Conclusions

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