Resistive random-access memory based on ratioed memristors

Abstract

Resistive random-access memories made from memristor crossbar arrays could provide the next generation of non-volatile memories. However, integrating large memristor crossbar arrays is challenging due to the high power consumption that originates from leakage currents (known as the sneak-path problem) and the large device-to-device and cycle-to-cycle variations of memristors. Here we report a memory cell comprised of two serially connected memristors and a minimum-sized transistor. With this approach, we use the ratio of the resistances of the memristors to encode information, rather than the absolute resistance of a single memristor, as is traditionally used in resistive-based memories. The minimum-sized transistor, which is connected to the midpoint between the two series-connected memristors, is used to sense the voltage to read the state of the cell and to assist with write operations. Our memory cell design solves the sneak-path problem and, compared to the traditional resistance-based current sensing approach for memory reads, our ratio-based voltage sensing scheme is more robust and less prone to data errors caused by variations in memristors. Device-to-device and cycle-to-cycle variations and leakage in memristor crossbar arrays can be alleviated with a memory cell design that uses the ratio of the resistances of two memristors to encode information, rather than the absolute resistance of a single memristor.