Residue codes for error correction in a combined decimal/binary redundant floating point adder

Abstract

As fault rates increase when technology advances from one node to another, fault tolerance becomes vital for the reliability of arithmetic circuits. This work represents an attempt to achieve fault tolerance for a combined IEEE decimal-64/binary-64 floating point redundant adder by using residue codes. To our knowledge, this is the first implementation of a residue error correction scheme in decimal and binary arithmetic circuits. The proposed circuit has the ability of all-digit error correction assuming that errors occur only in the main adder.