Abstract
High-performance superscalar processors, which can be used in building base-stations of cell phones and cloud-based web servers, rely heavily on aggressive branch predictors to avoid stalls no matter the branch is taken or not. Dynamic branch predictor which is based on the historical records of the previously executed branches always outputs good performance. Two-bit predictor discussed in this paper is one of the most popular ones that always practically employed. This paper demonstrates two implementations of two-bit predictors. Using BTB to process solo conditional branches is the first one, which is normally used. Other categories of branch instructions may results in several bubbles as the penalty. While the other implementation employs BTB dealing with all kinds of branch instructions, generating target addresses without any delay cycle. Simulation results show that the second implementation has much better performance than the former one. It decreases the mis-prediction rate from 12.26% to 11.48%, and also has much higher prediction accuracy on indirect jumps. With these results, we have our predictor re-designed accordingly and implemented successfully in superscalar processors.
Highlights
Nowadays, base-stations of mobile system and their cloud-based web servers rely heavily on high-performance processors
Branch prediction strategies [5] can be divided into two basic categories, depending on whether or not past history is used for making a prediction
While the dynamic branch prediction can dynamically alter the branch prediction depends on the past history
Summary
Base-stations of mobile system and their cloud-based web servers rely heavily on high-performance processors. Static branch prediction can not make use of the past history. Two-bit Prediction [5], which is one of the most traditional methods, has been widely used in practice Several multiprocessors such as PowerPC 604, MIPS R10000, Cyrix 6x86, take use of the two-bit predictors and achieve high-performance. One is by assigning two bits to each entry of the Branch Target Buffer (BTB) Another is use a separate Branch History Table (BHT) to conserve the counter values. Two-bit predictor’s advantages are easy to implement and has a low hardware delay, but it always holds lower prediction accuracy than two-level predictor and hybrid predictor. We expose the implementations details of the two different two-bit predictors, including the elements and prediction algorithm. The two-bit predictors’ implementations are based on alpha ISA
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