Abstract
The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-22 Single-path Delay Feedback (R22SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R22SDF algorithm; R22SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation. (5 pages)
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
