Research on parallel convolution algorithm for radar excitation signal of arbitrary length

Abstract

In the process of real-time generation of scene echo signals in the synthetic aperture radar real-time closed-loop echo simulator, a convolution is required every time an echo calculation parameter data packet is received. The number of points for convolution of the radar excitation signal and the target response function is relatively large, and the amount of calculation is large, which poses a challenge to the design of the system. The traditional convolution operation consumes a lot of resources and time when implemented in hardware, and cannot meet the requirements of the design. This design adopts a segmented parallel convolution algorithm to give full play to the advantages of FPGA parallel processing. Multiple pipelines are performed at the same time, which saves the time required for convolution operations. In order to solve the problem of the uncertain length of the radar excitation signal, this design proposes a time-sharing loop superposition algorithm, which successfully completes the convolution operation of the arbitrary-length radar excitation signal and the fixed-length target response function. The Xilinx FPGA development tool System Generator on the Simulink platform is used to build the model, and the circuit design is directly generated in the FPGA. Comparing the hardware test results with the theoretical results of Matlab simulation, it is found that they are basically the same. The parallel convolution algorithm proposed in this paper can accurately obtain the convolution result. At the same time, by evaluating the calculation time, the algorithm has good real-time performance and can meet the real-time requirements in radar echo simulation.