Research on global register allocation for code containing array‐unit dual‐usage register names

Abstract

SummaryArray‐unit dual‐usage register is a kind of register resource that can be read or written as a whole or individually. It is mainly configured in processors with SIMD processing units and provides register‐level speed data transfer between the scalar and vector processing units. To improve the efficiency of algorithms by using an array‐unit dual‐usage register, we investigate in this article the problem of adapting register allocation to code containing array‐unit dual‐usage register names. We propose a corresponding global register allocation method by combining the allocation of regular registers with array‐unit dual‐usage register, ensuring that the names of array‐unit dual‐usage register can be used in the input code of register allocation. Moreover, we present the processing framework of this method and the specific algorithms of some related vital aspects and demonstrate the working principles of the algorithms by an example. Experimental studies were conducted on a platform based on the FT‐M7002 DSP core, and showing that our register allocation method can effectively handle codes containing array‐unit dual‐usage register names and support relevant application algorithms to improve their data transfer scheme. For some typical algorithms with input matrix, substantial performance improvements of twofold or higher are achieved.