Research on Dynamic Reconfigurable Convolutional Neural Network Accelerator

Abstract

The hardware implementation of convolutional neural network has the problem of resource limitation, which can be solved by the design of convolutional neural network accelerator based on FPGA dynamic reconstruction. The whole parallel strategy and architecture of CNN accelerator are designed, and the functional modules of CNN are designed based on pipeline. The dynamic reconstruction technology is used to redesign the convolutional neural network accelerator, and the dynamic reconstruction region and division are established; BPI flash is selected to store the configuration file, and the configuration file is read internally to dynamically configure the dynamic reconstruction area. Finally, for lenet. 5 handwriting recognition, compared with the corresponding static design, the use of slice LUTS, slice registers and DSP resources of the accelerator based on dynamic reconstruction design is reduced by 46%, 25% and 68% respectively. Compared with the implementation based on software platform. The system execution time is greatly reduced. However, due to the bandwidth limitation of the internal configuration port, the reconfiguration configuration time prolongs the execution time of the whole convolutional network.