Research of timing graph traversal algorithm in static timing analysis based on FPGA

Abstract

This paper is a study to the application of graph traversal algorithms in static Timing Analysis (STA) module of Electronic Design Automation(EDA) tool. After Field Programmable Gate Array (FPGA) read into the design circuit, it replaces circuit with UDM (Universal Design Methodology) netlist internally. STA module does not work directly on the netlist, but converts the netlist to timing graph that only saves information related to timing. The timing graph consists of nodes and edges, nodes correspond to component pins or input and output ports, and edges are used to connect nodes, Edges have weights attached to them that can denote some characteristics, such as timing arc delays in this case[1]. There are two basic graph traversal algorithms: Depth First Search (DFS) and Breadth First Search (BFS). In this paper, two algorithms are applied to STA module and compared the runtime efficiencies by testing a large number of sequential circuit instances. The conclusion is that BFS algorithm can implement STA module more efficiently than DFS algorithm.