Research of Configurable Hybrid Memory Architecture for Big Data Processing

Abstract

A configurable hybrid memory architecture (CHMA) for big data processing is proposed in this paper. It includes computing nodes and memory nodes. The computing node can be configured according to the requirement of different applications to improve the applicability of the computing system. The memory node contains the memory control chip and memory network that support to build memory system with different type of memory devices. Each memory control chip contains two memory controllers. Two key technologies are proposed to optimize the bandwidth and latency of memory access for CHMA, one is the multi-channel parallel bus structure, and the other is the cache or buffer structure inserted in memory control chip. Experimental results show that: first, two memory controller are integrated in the memory control chip can maximize the bandwidth efficiency of the memory network; second, the bandwidth of multi-channel parallel bus is balanced with the bandwidth of two memory channels; third, when the cache or buffer structure is inserted in memory control chip, the latency of memory access is reduced and the bandwidth of memory access is improved, the memory access bandwidth of 64-thread stream OpenMP program is increased by 16.86% and the execution speed of NPB-MPI scientific computing applications are improved by an average of 6%.