Abstract
Digital Up-conversion is the core technology in digital radar transmitter. With the demand on the performance and functionality of digital radar transmitter increases highly, it is particularly necessary to develop high-efficient up-conversion technology. Multi-DDS algorithm proposed in this paper combines parallel processing thinking with theory of Direct Digital Synthesizer and utilizes the simultaneous operation of multiple traditional DDS unit. Meanwhile, it takes advantage of rich logic resources in FPGA to achieve IF signal with large bandwidth, high sampling rate on a low clock hardware platform.
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