Research and analysis of FIFO related working principles

Abstract

An asynchronous FIFO is a classic circuit device used for caching data and accommodating the frequency of asynchronous signals. With the continuous improvement of technology, the advantages of this device in real-time transmission, multi-core processing, and data acquisition have become more apparent. As a result, the original structure has been optimized and extended using algorithm and design techniques to achieve greater efficiency and applicability in various academic and industrial applications. This article discusses several methods for optimizing FIFO in different aspects and examines how an unlocked FIFO queue is applied in a CAN bus data acquisition system, as well as its use in data hybrid framing technology. The findings show that FIFO performs exceptionally well as a cache structure, particularly in situations involving large amounts of data acquisition and real-time procession. The various optimization techniques discussed in this article include using pipeline registers, implementing a dual-clock FIFO, and employing Gray-code-based pointers. These techniques can increase the speed and reduce the power consumption of FIFO, thereby improving its overall efficiency. In addition, the article introduces the unlocked FIFO queue, which provides more flexibility than conventional locked FIFOs. Unlocked FIFO queues allow multiple cores to access the buffer simultaneously, which makes them ideal for high-performance systems. Finally, the article explores the application of FIFO in CAN bus data acquisition systems, where it is utilized as a buffer between the bus and other devices. Additionally, the use of FIFO in data hybrid framing technology is discussed, where it is essential for maintaining the integrity of the data stream.