Representations for a rule based assistant for designing combinational circuits

Abstract

A rule based assistant for designing combinational logic circuits is described. The input can be described in terms of truth tables, logic equations, non-logic equations using arithmetic and relational operators or a combination of these three. The Strategist analyzes the input and decides on a particular implementation. It uses a set of rules to select a Read Only Memory (ROM), Programmable Logic Array (PLA) or a Random Logic (RL) implementation. The Constructor synthesizes RL circuits given an input description in a suitable form. Using its own set of rules, it detects and attempts to correct constraint violations which are specified in terms of speed, space and power. The hardware elements are chosen from a cell library. The system is designed to be highly extensible so that new rules can be added to the Strategist and the Constructor to make them more sophisticated. Figure 1 illustrates the relationship between the various building blocks of this system