Abstract
In this paper, the electrical parameter degradations of high-voltage 4H-SiC MOSFETs under repetitive unclamped-inductive-switching (UIS) stresses were investigated experimentally. The holes injection and trapping into the gate oxide above the JFET region is identified to be the main degradation mechanism, resulting in the increase of OFF-state drain–source leakage current ( $I_{\mathrm {DSS}})$ and the decrease of ON-state resistance ( $R_{\mathrm {dson}})$ . However, during the repetitive UIS stresses, there is not obvious degradation observed for the threshold voltage ( $V_{\mathrm {th}})$ of the device. Moreover, three improved SiC MOSFETs structures, one with step gate oxide above the JFET region, one with step p-body region, and another one with floated shallow p-well in the middle of JFET region, were proposed to reduce the degradations under the repetitive UIS stresses.
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