Repeater and interconnect strategies for high-performance physical designs

Abstract

Repeater insertion in interconnects is an increasingly important element in the physical design of high-performance VLSI systems. Interconnect tuning and repeater insertion are necessary to optimize interconnect delay, signal performance and integrity, and interconnect manufacturability and reliability. Our work provides the technology-specific studies of interconnect tuning and repeater insertion in the literature. We focus on global wiring layers and interconnect tuning issues related to repeater insertion and choice of shielding/spacing rules for signal integrity and performance. In this paper, we address the following issues: (1) For a given process, what criteria (or parameters) affect the optimal number of repeaters, optimal repeater size, and optimal repeater insertion length? (2) With repeater insertion we show that total delay becomes a linear function of total path length. (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? The conclusions and results obtained in this paper can be used in the analysis and optimization phase of synthesis and placement/route tools.