Reliable N sleep shuffled phase damping design for ground bouncing noise mitigation

Abstract

Power gating technique is one of the most effective techniques to reduce the leakage power in complex arithmetic logic circuits. But this leakage power reduction technique induces some severe ground bouncing noise during mode transition. To mitigate these issues, in this paper N-Sleep Shuffled Phase Damping (NSSPD) technique is introduced which attains an increased reliability with high energy efficiency. 16-bit Carry Select Adder is designed using 1-bit NSSPD full adder which is a hybrid combination of staggered phase damping and parallel sleep transistor technique for suppressing ground to rail fluctuations, leakage power and to improve lifetime reliability of today's integrated systems. The proposed NSSPD technique is designed and simulated in tanner EDA with 125 nm CMOS technology. The experimental results show that proposed NSSPD technique reduces the power consumption, energy consumption and leakage power to 12%, 21% and 14.56% when compared to the previous super stacking ground bounce noise reduction technique.