Abstract
In most of the digital signal processors, multiplier is used as a key component. So, the performance of the system depends on the throughput of the multiplier. Now a days, relia-bility is an important design concern in advanced technology nodes. Performance of the system is significantly affected by the aging of transistor and the system may fail due to delay problems in long term. The impact of aging getting higher with the scaling of transistor. One of the main cause for aging in transistor is Bi-as Temperature Instability (BTI). Due to this effect threshold voltage of the transistor increases over time and it reduces the multiplier speed. Over-design approaches can be used to reduce the aging effect, but these may cause power and area inefficiency. Fixed latency designs have high chance of timing violations. So, a multiplier with variable latency is used for reliable operation under BTI effects. An Adaptive Hold Logic (AHL) is used for the proper selection of cycle period and an Error Detection Correction Pulsed Latch (ECPL) is used for the detection of timing errors.
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