Abstract
The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of the ATLAS Tile Calorimeter. This will allow the proposed upgrade to be thoroughly evaluated well before the planned 2023 deployment in all slices, especially with regard to long term reliability. Different firmware strategies alongside with their integration in the demonstrator are presented in the context of high reliability protection against hardware malfunction and radiation induced errors.
Highlights
THE ATLAS Tile Calorimeter (TileCal) [2] is partitioned into 4 cylindrical sections, each composed of 64 wedge shaped modules
Accelerated life testing of neutron damage is scheduled for summer 2014, along with other components of the demonstrator
The Single event upsets (SEUs) tests of the daughter board have been performed at Massachusetts General Hospital (MGH) Francis H
Summary
THE ATLAS Tile Calorimeter (TileCal) [2] is partitioned into 4 cylindrical sections, each composed of 64 wedge shaped modules. In the upgraded Tile Calorimeter electronics planned for 2023, PMT data for all LHC bunch crossings will be read out to the off-detector electronics [4], allowing the Level-1 trigger selection to make use of cell-by-cell digital processing, in contrast to the current pre-summed analog towers. This will help reduce the effect of minimum bias pileup on triggering, which is expected to be a considerable problem in high luminosity operations. The logic is implemented in Kintex-7 FPGAs [7] with elaborate error mitigation techniques to be able to recover from radiation-induced errors
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
