Reliability Simulation Models for Hot Carrier Degradation

Abstract

Because reliability considerations are gradually shifting from device to circuit level (Groeseneken et al., Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies, Proceedings of the ESSDERC, 2010, pp. 64–72), circuit reliability simulation is becoming increasingly important. To enable reliability simulation, reliability simulation models are a prerequisite. These simulation models are often based on analytical descriptions taken from the literature. Apart from the desire to make these models fit experimental data accurately, one encounters some specific practical problems when building them. These problems include (1) the translation from equations derived for DC stress conditions to equations valid under more general transient stress conditions, (2) the translation of the degradation of observables to the degradation of compact model parameters, and (3) the need to keep the simulation overhead of these models to the bare minimum. These issues will be addressed in this chapter, and illustrated using the examples of (1) reverse-V BE degradation in HBTs, (2) hot-carrier degradation in MOSFETs, and (3) hot-carrier degradation in LDMOS devices.