Abstract
The rate of defect generation by electrical stress in silicon dioxide has been measured as a function of gate voltage down to 2 V on a variety of MOSFETs with thickness in the range 1.4-5 nm. The critical defect density necessary for destructive breakdown has also been measured in this thickness range. These quantities are used to predict time to breakdown for ultra thin oxides at low voltages. The properties of the breakdown distribution, which becomes broader as the oxide thickness is reduced, are used to provide reliability projections for the total gate area on a chip. It is predicted that oxide reliability may limit oxide scaling to about 2.6 nm (CV extrapolated thickness) or 2.2 nm (QM thickness) for a 1 V supply voltage at room temperature and that the current SIA roadmap will be unattainable for reliability reasons by sometime early next century.
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