Abstract

The reliability of 6-10 nm SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films is investigated on 0.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS capacitors with polycrystalline silicon electrode in terms of dielectric breakdown. The SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films prepared show intrinsic dielectric integrity, that is, time-zero dielectric breakdown field for all capacitors distributes sharply around 10 MV/cm. Accelerated time dependent dielectric breakdown (TDDB) is examined. Electric field acceleration factor and temperature acceleration factor are evaluated. Using these factors, the failure rate for 6-10 nm SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> is estimated to be less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 \times 10^{-8}</tex> /hour under a 5 MV/cm at 150°C operating condition. It is concluded that the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films with intrinsic time-zero dielectric breakdown behavior are highly reliable with regard to TDDB and the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films as thin as 6 nm are assured to be applicable to VLSI devices.

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