Abstract
To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed.
Highlights
The complementary metal-oxide-semiconductor (CMOS) technology is the cornerstone of a vast number of integrated circuits, which are the building blocks of numerous electronic applications
While the source-current exhibits a continuous drift at large-area devices, charge trapping evolves in discrete steps of the device current, recorded at nanoscale MOS transistors. This is due to the fact that scaling of the devices on the one hand reduces the number of defects per device, but on the other hand the impact of a single defect on the overall device behavior gets considerably increased
Results from single defect studies performed on nanoscale devices are discussed in detail
Summary
The complementary metal-oxide-semiconductor (CMOS) technology is the cornerstone of a vast number of integrated circuits, which are the building blocks of numerous electronic applications. The reduced mobility evolves as a reduction in the sub-threshold slope and can be for instance observed when IDVG measurements are performed [16,17], but can be evaluated as the CV characteristics of the device alters [18] Another important reliability issue in miniaturized devices is the so called bias temperature instabilities (BTI) [19,20,21,22,23,24]. While the source-current exhibits a continuous drift at large-area devices, charge trapping evolves in discrete steps of the device current, recorded at nanoscale MOS transistors This is due to the fact that scaling of the devices on the one hand reduces the number of defects per device, but on the other hand the impact of a single defect on the overall device behavior gets considerably increased. Afterwards the TDDS is presented and charge trapping models and recent results from single defect studies are reviewed
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