Relaxation Oscillator With Dynamic Comparator and Slope-Boosting Technique

Abstract

This brief presents a low-power low-jitter relaxation oscillator for on-chip low-frequency clock generation. A dynamic common-gate comparator is proposed to reduce the power, combined with a slope boosting technique to reduce the period jitter. A peak-detecting feedback loop is implemented to maintain frequency stability over temperature variations. The oscillator achieves 0.025% period jitter and 70 ppm/°C temperature coefficient while consuming 1.36 $\mu \text{W}$ at 364 kHz with a 1.2-V supply.