Relationship between settling time and pole–zero placements for three-stage CMOS opamp

Abstract

In this article, the effect of pole–zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole–zero placements and settling time. The study of the effects of compensation elements on pole–zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole–zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17 µw and a settling time of 340 ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.