Abstract
By relating the complete spatial interface trap profile to the variation of electrical parameters in n-channel LDD and FOND MOSFET's, we clarify the respective role of defects above the channel and the LDD region. We show that the saturation of the series resistance increase is due to the leveling off of the rate of interface trap generation and not to the self-limiting impact of such defects on the series resistance. The importance of the choice of the parameter used to estimate the lifetime is demonstrated.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
