Relating Friction and Processes Development during Chemical — Mechanical Polishing (CMP)

Abstract

Die-scale models of CMP have been previously reported for a number of different CMP processes used in integrated circuit (IC) manufacturing, including oxide, dual material shall row trench isolation, and dual material copper damascene processes. Next generation integrated circuits (IC’s) will require the use of porous dielectric materials with shear strengths much lower than the currently used dense silicon dioxide. The high friction of CMP may damage these porous dielectric materials. This research is being performed to define the nanoscale source of this poorly understood CMP friction to enable development of less damaging CMP processes. It is proposed that the nanoscale friction on the IC from CMP is a variable combination of two-body pad nano asperity to IC contact and three-body nanocontact of the slurry particles between the pad nano asperity and the IC surface.