Regular fabric for regular FPGA (abstract only)

Abstract

In the sub-wavelength regime, design for manufacturability (DFM) becomes increasingly important for field programmable gate arrays (FPGAs). In this paper, we report an automated tile generation flow targeting micro-regular fabric, this flow automatically generate the basic FPGA tile building block in a standard cell format and then form the whole tile with the help of commercial placing and routing tools. Using a publicly accessible, well-documented academic FPGA as case study, we found that comparing to the tile generators previously reported, our generated micro-regular tile incurs less than 10% area overhead, which could be potentially recovered by process window optimization thanks to its superior printability. In addition, we demonstrate that on 45nm technology, the generated FPGA tile reduces lithography induced process variation by 33%; and reduce probability of failure by 21.2%. If further overhead of 10% area can be recovered by enhanced resolution, we can achieve the variation reduction of 93.8% and reduce probability of failure by 16.2%.