Abstract
Software to support the Monte Carlo method generates large vectors of pseudo-random numbers and uses these as operands in complex mathematical expressions. When such software is run on standard PC-based hardware, the volume of data involved often exceeds the physical RAM available. To address this problem, vectors must be paged out to disk and paged back in when required. This paging is often the performance bottleneck limiting the execution speed of the software. Because the mathematical expressions are specified in advance of execution, predictive solutions are possible – for instance, by treating the problem similarly to register allocation. The problem of allocating scalar variables to processor registers is a widely studied aspect of compiler implementation. A register allocation algorithm decides which variable is held in which register, when the value in a register can be overwritten, and when a value is stored in, or later retrieved from, main memory. In this paper, register allocation techniques are used to plan the paging of vectors in Monte Carlo software. Two register allocation algorithms are applied to invented vector programs written in a prototype low-level vector language and the results are compared.
Highlights
In the Monte Carlo method, a random sample of inputs is fed through a deterministic set of computations
Tian and Benkrid [2] demonstrated the use of field-programmable gate arrays (FPGAs) to speed up a Monte Carlo simulation, but the need for specialized hardware limits the commercial relevance of the findings
The Monte Carlo models considered here perform deterministic computations which are defined in advance of the model run, making it possible to predict when values will be required in memory, when they can be paged to disk, and what the performance impact of paging would be
Summary
In the Monte Carlo method, a random sample of inputs is fed through a deterministic set of computations. One problem that arises when implementing such software is that the volume of data involved in the computations exceeds the physical RAM available on the host This leads to vectors of values being paged out to disk to make more memory available, and a particular vector is paged back in when it is required for a later stage of computation. Tian and Benkrid [2] demonstrated the use of field-programmable gate arrays (FPGAs) to speed up a Monte Carlo simulation, but the need for specialized hardware limits the commercial relevance of the findings. This project assumes that the software will run on a conventional PC or server. The conclusion (section 8) summarises the findings and suggests further research
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