Regional cache organization for NoC based many-core processors

Abstract

As the number of Processing Elements (PEs) on a single chip keeps growing, we are now facing with slower memory references due to longer wire delay, intenser on-chip resource contention and higher network traffic congestion. Network on Chip (NoC) is now considered as a promising paradigm of inter-core connection for future many-core processors. In this paper, we examined how the regional cache organizations drastically reduce the average network latency, and proposed a regional cache architecture with Delegate Memory Management Units (D-MMUs) for NoC based processors. Experiments showed that the L2 cache access latency is largely determined by its organization and inter-connection paradigm with PEs in the NoC, and that the regional organization is essentially important for better NoC cache performance.