Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

Roman Golman,Robert Giterman,Adam Teman,Netanel Nachum,Tomer Cohen

doi:10.1109/access.2021.3099970

Abstract

Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. In this work we propose a memory architecture based on a novel refreshing algorithm that provides 100% memory availability for the user, resulting in no performance loss for any possible access pattern. This approach allows the memory to have a standard SRAM interface (“vanilla interface”), supporting direct replacement of the SRAM memory with a GC-eDRAM memory. The algorithm/architecture was implemented in a 65 nm CMOS technology resulting in more than 20% area reduction compared with standard SRAM solutions, for large memory implementations.

Highlights

Modern integrated circuit (IC) chips consist of billions of transistors, with the majority of the chip area utilized for the implementation of embedded memory blocks
3) The analysis shows that the use of GC-eDRAM instead of static random access memory (SRAM) still leads to a 20% reduction in area, despite the overhead introduced by the proposed memory controller and additional hardware
REQUIRED NUMBER OF COIS The previous section pointed out two scenarios, which could prolong the refresh operation on a sub-bank indefinitely: user reads during the read phase and user writes during the write-back phase

Summary

INTRODUCTION

Modern integrated circuit (IC) chips consist of billions of transistors, with the majority of the chip area utilized for the implementation of embedded memory blocks. To the best of our knowledge, we propose the first algorithm to ensure 100% availability for GC-eDRAM macros in the random access case, without inferring pipelined operation This capability enables the drop-in replacement of single-ported static random access memory (SRAM) based memory implementation with the proposed GC-eDRAM architecture and controller, without requiring any system changes or incurring any performance loss. The proposed algorithm can be used for memories based on the basic 2T bitcell, and for other types of GC-eDRAM bitcells, such as the ones described in [18], [19] allowing to optimize for area and power These cells operate on similar principles, offering slightly different write and read port constitutions, providing better retention time or more robust read [20]. The methods for handing these cases are described hereafter and implemented in the algorithms for the read and write-back phases provided in Algorithm 1 and Algorithm 2, respectively

A READ ACCESS DURING THE READ PHASE

REQUIRED NUMBER OF COIS

IMPLEMENTATION AND AREA OVERHEAD

Findings

CONCLUSION