Refinement-based formal verification with heterogeneous timing

Abstract

In this paper we propose a refinement-based technique to formally verify data transfer in a heterogeneous timing framework. Novel data transfer models are proposed to represent data communication between two locally independent clock domains via an asynchronous handshake environment. As a case study, we apply our technique to automatically verify data transfer in a previously published architecture for globally asynchronous locally synchronous on-chip systems. In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected dangers.