Abstract
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper investigates how gate height <formula formulatype="inline"><tex Notation="TeX">$(H_{g})$</tex></formula>, which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower <formula formulatype="inline"><tex Notation="TeX">$H_{g}$</tex></formula> yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower <formula formulatype="inline"><tex Notation="TeX">$H_{g}$</tex></formula> shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM. </para>
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