Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Luis Miguel Carvalho Freitas ,Fernando Morgado‐Dias

doi:10.3390/electronics10030299

Luis Miguel Carvalho Freitas , Fernando Morgado‐Dias

Open Access

https://doi.org/10.3390/electronics10030299

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Journal: Electronics	Publication Date: Jan 27, 2021
Citations: 2	License type: CC BY 4.0

Affiliation: Madeira Tecnopolo, Universidade da Madeira

Abstract

Modern Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, aimed to target low-noise and fast digital outputs, are fundamentally based on column-parallel structures, jointly designed with oversampling column converters. The typical choice for the employed column converters is the incremental sigma-delta structures, which intrinsically perform the correlated multiple sampling, creating an averaging effect over the system thermal noise when used in conjunction with 4T-pinned pixels. However, these types of column converters are known to be power-hungry, especially if the imaging device needs to target high frame rate levels as well. In this sense, the aim of this paper was to address the excess of power dissipation problem that arises from image sensors while employing oversampling high-order incremental converters, by means of using a different connection scheme to supply and to drive the required reference signals across the image sensor on-chip column converters. The proposed connection scheme revealed to be fully functional with no unwanted artifacts in the imager output response, allowing it to avoid 20% to 50% of the power dissipation, relative to the classical on-chip references generation and driving method. Furthermore, this solution allows for a much less complicated and less crowded printed circuit board (PCB) system.

Highlights

Recent developments with regards to the optimization of the column readout circuits, in parallel with the improvements on the pixel design, namely sensors using pinned-pixels, in-pixel amplification, and pixel-process optimization, have led to the appearance of a new class of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CIS) that can detect and manage light at extremely low levels of illumination
It is commonly found in the literature that to achieve a low-noise pixel/column readout circuit, the correlated multiple sampling (CMS) technique must be employed [7,8,9,10]
The choice of an analog voltage supply lower than 3.3 V becomes effective knowing that, for a high-order analog-to-digital converters (ADCs) modulator, the current consumption portion of the modulator lies in the range of approximately 55% of the entire per-column readout circuit current consumption, yet excluding the partial amount for the references generation consumption

Summary

Introduction

Recent developments with regards to the optimization of the column readout circuits, in parallel with the improvements on the pixel design, namely sensors using pinned-pixels, in-pixel amplification, and pixel-process optimization, have led to the appearance of a new class of CMOS image sensors (CIS) that can detect and manage light at extremely low levels of illumination. The present research project focused on low-noise design, high FR, and high-resolution CIS devices, targeted for a possible future development with a 3D stacked CIS implementation in mind, to target high-end applications such as for industrial and scientific areas. In this sense, this paper deepens the work from the same authors regarding the CIS test chip development [3,4], as well as both its fabrication and characterization work [5,6].

Background

Problem Description

Proposed Low-Power References Supply Cost-Effective Solution

Findings

Conclusions