Redundancy Pruning for Binary Hyperdimensional Computing Architectures

Abstract

Hyperdimensional computing (HDC) is an emerging memory-centric computing paradigm that uses vectors with very high dimensions as distributed representations in associative memories. HDC architectures are energy-efficient compared to conventional artificial neural networks because it uses simple operations. However, HDC architectures still contain massive bitwise operations and a large memory footprint. Current optimizations often reduce dimensions to consume lower energy at the cost of degraded accuracy. In this work, we propose pruning redundant bits in the associative memory because these bits do not contribute any information during classification. Reducing these irrelevant bit-wise operations results in significant energy savings without sacrificing accuracy. We tested the pruning of redundant bits on three applications: character recognition, hand-written digits recognition, and DNA sequencing classification problems. We achieved a speedup of 1.2x-3.4x and 14%-66% energy savings per prediction at the cost of a 6.4%-17.9% increase in area.