Reduction of Zero-Sequence and Differential-Mode Circulating Currents and Common-Mode Voltage in Parallel PWM Converters

Abstract

This paper aims to present a reduction strategy for circulating current and common mode voltage in parallel PWM converters. As the common mode voltage reduction is possible only with the elimination of some switching vectors, it may affect the circulating current paths. Elimination of both mentioned parameters at the same time is impossible for the systems with two-level converters. Therefore, in addition to the modification of the PWM strategy, an interface circuit is introduced to reduce the circulating current as well as reducing current ripple and losses. This topological modification adds some degree of freedom and leads to a reduction of circulating currents passing through each switch which releases its current carrying capability and reducing conduction losses especially in higher power and voltage applications. Simulation and experimental results are presented to verify the analysis of the proposed strategy.