Abstract
This article presents a method for test data compression aiming at simultaneously reducing test data volume and test application time for the scan sequential circuits. Compatible columns in the test set are repeatedly merged such that test data in the corresponding scan cells can be shared. To decode the compressed test data, a scan chain disabling technique is employed. Experimental results for the large ISCAS’89 benchmarks have demonstrated that significant reductions in both test data volume and test application time can be achieved.
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