Reduction of short circuit current in static CMOS inverters using novel smart delay generator circuits

Abstract

CMOS inverters have the advantage of zero static power consumption. However, they suffer from dynamic power consumption and short circuit power consumption. Dynamic power consumption results from charging the output capacitance then discharging it again. Whereas short circuit power consumption happens during the switching of the inverter between logic '1' and logic '0' due to the direct current path that opens between V DD and Ground for the duration of the inverter switching. The problem of short circuit current is not only the amount of power consumption but also its contribution to the noise in the supply by adding unnecessary rebels to the supply current. This paper introduces two different novel and simple smart delay generator circuits that will reduce the amount of short circuit current in CMOS inverters by more than 50%.