REDUCTION OF POWER CONSUMPTION IN THE SRAM SENSE AMPLIFIER

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Power reduction is one of the primary problems in modern high-speed integrated circuits. Static RAM is one of the most common type of memory. The average power consumption and speed of the SRAM device have a great impact on the performance of the whole system. In SRAM, a sense amplifier is considered to be an active element in the reading process. Besides, the moderate decrement of the average power consumption in the sense amplifier can cause a significant power reduction of the entire system, as bit lines in SRAM are connected to sense amplifiers. The existing sense amplifier of SRAM is investigated in this paper. The transistors of the selected amplifier are changed by ultra-low-voltage transistors. Also, the design of current mirrors is changed. The proposed circuit has fewer active transistors, which reduces the power consumption of the sense amplifier in the reading process. The circuit is designed with 28 nm and 14 nm (FinFET) technology and examined according to power consumption and sensitivity. As the parameters of the amplifier can vary with different technological processes, the scheme has been optimized for different technological processes (typical, fast, slow, etc.). The results of the scheme simulation at different temperatures and supply voltages are presented. A comparative analysis of the selected and proposed schemes is performed according to the average power consumption.