Reduction of energy consumption using SPM and optimal code layout in embedded systems

Abstract

In the multiprocessing embedded system the efficient use of the on-chip and off-chip memory code repositioning is done. For the purpose of improvement in the embedded system the SPM and cache is used for the code processing. The code layout is developed to place the code in memory for the preventing the cache conflicts and misses. Even though many researchers have illustrated the use of SPM and cache to improve the efficiency, combining these two was not done. In this study the comparison of energy consumption is done while code processing is done by three models namely 1) ILP model 2) Heuristic model 3) two stage meta-heuristic model. In the above two stage Meta heuristic model is the proposed model in which along with the SPM and Cache code layout is developed to place the code in it. The result reveals that compared to other two models the two stage meta-heuristic model yield more efficiency and consume less energy than other two models. As much as approximately 55% of additional energy can be saved by applying both code repositioning and SPM code selection techniques in this model.