Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking

Abstract

The reduction of defects and high-speed copper filling into a through-silicon-via (TSV) for the three-dimensional stacking of Si chips were investigated. The via, with a diameter and depth of 30 μm and 60 μm, respectively, was prepared on a Si wafer by a deep reactive ion etching (DRIE) process. SiO 2, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a 3-step periodic-pulse-reverse (PPR) current waveform was suggested for electroplating. The 3-step PPR consisted of low, medium and high current densities for the 1st, 2nd and 3rd steps, respectively. After Cu filling, in order to estimate defects in the Cu-filling, the via was cross-sectioned and observed by field emission scanning electron microscopy (FE-SEM), and also an X-ray radiographic test was performed for non-destructive inspection. The experimental results showed the via was fully filled without a serious defect by the 3-step PPR process after 80 min of plating, specifically, by current densities of −1.24, −3.22, and −9.89 mA/cm 2 (1st/2nd/3rd step, respectively). The 3-step PPR filling was a kind of bottom-up filling process of Cu into the via, and it was effective for Cu filling in a short time. Defects, like voids in the Cu-filled TSV, were identified by the X-ray radiographic test, which can be useful for ensuring the reliability of a fragile thin Si wafer for 3D packaging.