Reduction of “Dark-Gate” defects in replacement-metal-gate process and middle-of-line contacts for advanced planar CMOS and FinFET technology

Abstract

We systematically analyzed that the dark-gate defects were detected by e-beam and bright field inspection as one of the top yield limiters (i.e. the defects of gate-to-contact shorts/leakage) and correlated these to physical failure modes in multiple steps through RMG and MOL process steps. A few effective/novel solutions in the process steps are successfully demonstrated with planar CMOS technology, and are useful for robust RMG/MOL process and yield step-up with 128Mb SRAM/Logic for both planar CMOS and FinFET technology.