Abstract
Limit Cycle oscillation is a major issue in digitally controlled dc–dc converter due to low resolution digital pulse width modulators (DPWMs). This paper proposes a method for the reduction in limit cycle oscillation by combining the advantages of sigma delta modulation scheme and frequency modulation of switching frequency. In this paper, the correction of quantization error due to low resolution DPWM is accomplished by changing the switching frequency. The error due to the quantization of DPWM was accumulated for few clock cycles and the switching frequency was adjusted in the last cycle such that the duty ratio changes by the number of LSBs corresponding to the quantization error. The quantization error correction increases the effective resolution of DPWM thereby reducing the ripple due to limit cycle oscillations. Further, it also reduces the conducted electromagnetic emissions. Simulations using the SIMULINK model of the converter were carried out to validate the effectiveness of the proposed method. Experimental verification of the scheme was also carried out using a 16 bit DSP Processor which showed around 17 dB reduction in ripple due to limit cycle oscillation and 25 dB reduction in conducted emission levels.
Published Version
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