Reducing Worst Case Reaction Time of Synchronous Programs on Chip-multiprocessors with Application-Specific TDMA Scheduling

Abstract

The synchronous approach featuring deterministic concurrency is widely used to design and verify real-time embedded systems. The synchronous model of computation divides the execution of a program into discrete instants, called ticks. For correctly capturing all input events from the environment, it is pivotal to statically estimate the worst case tick length, also known as the worst case reaction time (WCRT) of synchronous programs. Plenty of techniques have been proposed for WCRT analysis of synchronous programs targeting uniprocessors, but little has been done for chip-multiprocessors (CMPs). Concurrent accesses to the shared bus of a CMP are managed by the bus arbitration policy for eliminating access contentions. The common time division multiple access (TDMA) approach equally divides the bus bandwidth amongst all processors in a CMP, and is oblivious to the bus access contention patterns, thus resulting in large WCRT overestimates. In this paper we propose an application-specific TDMA (ASTDMA) bus scheduling approach, which takes into account the bus access contention pattern of the application and results in shorter static WCRT estimates. Experimental results reveal that the ASTDMA approach achieves on average 21.33% shorter WCRT estimates compared to the standard TDMA scheduling policy.