Reducing the switching activity of test sequences under transparent-scan

Abstract

Transparent-scan is a test application scheme for scan circuits. It provides unique opportunities for test compaction that do not exist with the standard test application scheme. We show that it also provides unique opportunities for reducing the power dissipation of a scan-based test set. After translating a standard scan-based test set into a transparent-scan sequence, we apply two operations for reducing the power dissipation of the sequence. The first operation attempts to remove a test vector that causes high power dissipation. The second operation attempts to replace a scan clock cycle with a functional clock cycle, or a functional clock cycle with a scan clock cycle, in order to reduce the power dissipation. Both operations are implemented such that they reduce the power dissipation without reducing the fault coverage. We also consider a third operation that attempts to complement arbitrary values in the transparent-scan sequence in order to further reduce the power dissipation.