Reducing the power consumption of level-crossing analog-to-digital converters by using a signal activity monitoring circuit

Abstract

An activity monitoring circuit is proposed for reducing the activity and thus the power consumption of the synchronous level-crossing analog-to-digital converter. The proposed technique does not affect the output samples, the average sampling frequency, or the accuracy. Utilizing a floating-window structure, high accuracy is achieved while the suggested activity monitoring technique significantly reduces power consumption to levels comparable to the fixed-window structure. To show the effectiveness of the proposed structure, two converters are designed for ECG and neural signal acquisition in a 0.18 μm CMOS process. For ECG (Neural), the power consumption and the activity of the converter are decreased by 42.3 % (38.41 %) and 45.4 % (44.5 %), respectively. Post-layout simulation results show a power consumption of 26.8 nW and an effective number of bits (ENOB) of 9 bits for ECG application. The power consumption is 223.3 nW and the ENOB is 6 bits for neural application. This makes the proposed structure suitable for ultra-low power wearable and implantable biopotential-recording applications.