Reducing test application time, test data volume and test power through Virtual Chain Partition

Abstract

A new scan approach is described, named ‘Virtual Chain Partition’ (VCP) architecture, capable of substantially reducing the test application time, test data volume and test power. The VCP architecture maintains the original scan cell order. A simple procedure is proposed, which uses the scan test set generated for the original circuit to determine the maximum reduction in test cycles obtainable with the architecture and to select the most suitable configuration for each circuit. The experiments carried out with the ISCAS 89 benchmarks show that the VCP architecture allows considerable reductions to be achieved both for single and multiple scan chain circuits.