Reducing read latency in phase-change RAM-based main memory

Abstract

Phase-change RAM (PRAM) is considered to be a promising candidate to complement or replace DRAM which is expected to suffer from device scaling in near future. PRAM has the advantages of better scaling and non-volatility. However, PRAM suffers from write endurance and long latency. Differential write, where only modified bits are updated in memory, is required to reduce bit updates in PRAM to improve both write endurance and latency. Due to the constraint of peak write current in PRAM, write unit size is typically smaller than the row buffer size (the unit of precharge operation in conventional DRAM). Thus, write latency becomes a function of the amount of modified data bits. Read latency, which is more critical in system performance than write latency, is affected by such long and variable write latency in PRAM. In our work, we investigate a method of memory access scheduling for PRAM which applies write cancellation while taking into account variable write latency in differential writes in order to further improve read latency. Given the information of write latency, the proposed idea offers average 26% further improvement in PRAM read latency.